相信 IC designer 都知道, 一顆IC要能 tape-out, 其中一項關鍵因素就是 STA 要過關. 大家都知道STA 是 static timing analysis , 但是我發現很多人(甚至資深工程師)對timing的觀念不夠清楚. 在這裡我列出幾個重點觀念:
(1) setup time:
通常, 同一個clock domain的訊號在FF和FF之間傳遞時, 都不能超過一個clock cycle的時間 (除非design 本身設計是允許multi-cycle). 這是最基本的setup time的觀念. 而後面那級FF也會要求一個setup-time, 也就是說, 從前級FF的clock trigger 其output訊號toggle後, 經過一串combinational logics, 一直到後一級FF所允許的delay (CK to FF delay + combinational delay) 等於cycle time 減掉後級FF要求的 setup time. (這還是沒考慮skew的算法). 前後級的FF,其clock到達的時間會有點差異(skew), 這段timing path的setup time 可能會因為 skew的存在而變緊或變鬆一點. 所以有一種技術叫做usefull skew, 可以利用刻意調整的skew來放寬critical path. (將後級clock phase調後面一點或前級的clock phase 調前面一點)
(2) hold time:
一般人對hold time的觀念更不清楚. hold time 的問題大部份都是由skew造成的. 若前級FF的clock phase 比後級FF前面許多, 會造成前後級FF在同一個clock cycle toggle (就像訊號在一個cycle裡連跳兩級一樣). 除非是特殊設計, 一般的設計是不允許這樣的. 此外, 後級FF也會要求訊號在我的clock edge後需"hold"一段時間才可以. 因此, 即使前後級的clcok沒有skew, hold time還是不見得夠的. 所以有些FF的設計有負的hold time request (其內部多delay一點點data path), 只要skew控制的夠小, 其hold time就可以過關, 不需另外加delay 在前後級之間.
所以, 所有的timing path (FF to FF) 都需符合一個原則: delay不能太大但也不能太小.
(3) false path:
有些timing path因design的特性, 不見得要符合setup/hold time. 這些path就叫做false path. 最常見的就是不同clock domain 之間的訊號path. 從clock1 domain傳遞到clock2 domain時, 大多是不需看setup/hold time的. (除非design本身要求這兩個clock要有固定的相位關係)
exp:
ref:http://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html
neg hold time meaning
In a digital circuit, the hold time is the minimum time that an input signal must remain stable after the active edge of the clock in order to assure that that input is correctly recognized.
If a circuit has a negative hold time, this means that the input can change before the clock edge and nevertheless the old level will be correctly recognized. This can be produced by internal delay of the clock signal. For example, if a D flip flop has a hold time of –1ns, the level present at the D input up to 1 ns before the clock edge is the level captured, provided it was stable up to that moment.
Setup time is the minimum time that an input must stabilize to its logical level before the active edge of the clock in order to assure that that input is correctly recognized.
If a circuit has a negative setup time, this means that the input can change after the clock edge and nevertheless the new level will be correctly recognized. This can be produced by internal delay of the clock signal. For example, if a D flip flop has a setup time of –1ns, the level present at the D input from 1 ns after the clock edge is the level captured, provided it remains stable from that moment.
http://www.edaboard.com/thread7046.html
(1) setup time:
通常, 同一個clock domain的訊號在FF和FF之間傳遞時, 都不能超過一個clock cycle的時間 (除非design 本身設計是允許multi-cycle). 這是最基本的setup time的觀念. 而後面那級FF也會要求一個setup-time, 也就是說, 從前級FF的clock trigger 其output訊號toggle後, 經過一串combinational logics, 一直到後一級FF所允許的delay (CK to FF delay + combinational delay) 等於cycle time 減掉後級FF要求的 setup time. (這還是沒考慮skew的算法). 前後級的FF,其clock到達的時間會有點差異(skew), 這段timing path的setup time 可能會因為 skew的存在而變緊或變鬆一點. 所以有一種技術叫做usefull skew, 可以利用刻意調整的skew來放寬critical path. (將後級clock phase調後面一點或前級的clock phase 調前面一點)
(2) hold time:
一般人對hold time的觀念更不清楚. hold time 的問題大部份都是由skew造成的. 若前級FF的clock phase 比後級FF前面許多, 會造成前後級FF在同一個clock cycle toggle (就像訊號在一個cycle裡連跳兩級一樣). 除非是特殊設計, 一般的設計是不允許這樣的. 此外, 後級FF也會要求訊號在我的clock edge後需"hold"一段時間才可以. 因此, 即使前後級的clcok沒有skew, hold time還是不見得夠的. 所以有些FF的設計有負的hold time request (其內部多delay一點點data path), 只要skew控制的夠小, 其hold time就可以過關, 不需另外加delay 在前後級之間.
所以, 所有的timing path (FF to FF) 都需符合一個原則: delay不能太大但也不能太小.
(3) false path:
有些timing path因design的特性, 不見得要符合setup/hold time. 這些path就叫做false path. 最常見的就是不同clock domain 之間的訊號path. 從clock1 domain傳遞到clock2 domain時, 大多是不需看setup/hold time的. (除非design本身要求這兩個clock要有固定的相位關係)
exp:
neg hold time meaning
In a digital circuit, the hold time is the minimum time that an input signal must remain stable after the active edge of the clock in order to assure that that input is correctly recognized.
If a circuit has a negative hold time, this means that the input can change before the clock edge and nevertheless the old level will be correctly recognized. This can be produced by internal delay of the clock signal. For example, if a D flip flop has a hold time of –1ns, the level present at the D input up to 1 ns before the clock edge is the level captured, provided it was stable up to that moment.
Setup time is the minimum time that an input must stabilize to its logical level before the active edge of the clock in order to assure that that input is correctly recognized.
If a circuit has a negative setup time, this means that the input can change after the clock edge and nevertheless the new level will be correctly recognized. This can be produced by internal delay of the clock signal. For example, if a D flip flop has a setup time of –1ns, the level present at the D input from 1 ns after the clock edge is the level captured, provided it remains stable from that moment.
http://www.edaboard.com/thread7046.html
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